1. Field of the Invention
The present invention relates to devices and methods for fabricating integrated circuits, and in particular to devices and methods for fabricating heterojunction bipolar transistors wholly from silicon carbide and using germanium doping to produce suitable emitter/base heterojunctions.
2. Background of the Technology
High-efficiency power amplifiers (PA) operating from the VHF (0.1 GHz) to above X-band (( greater than 10 GHz) are critical components for next-generation military and civilian applications. Bipolar transistor topologies are often preferred over Field Effect Transistors (FETs) for many of those PA applications because of their excellent linearity and large gain at high frequencies, as well as a small noise figure, which is minimized at very low currents. Generally, bipolar transistors are electronic devices with two pn junctions in close proximity.
Power amplifier design in the best of circumstances is a challenging venture, but at high radio frequency (RF) and microwave frequencies and at high power densities, this is particularly true. Conventional silicon (Si) bipolar junction transistors (BJTs) cannot deliver adequate linearity, noise figure, and gain with useful breakdown voltage at such high frequencies. Heterojunction bipolar transistors (HBTs) are bipolar transistors having emitter materials with band gaps larger than that of the material used in the base. Heterojunction bipolar transistors comprised of III-V (i.e., gallium arsenide (GaAs)) have a number of benefits over Si based HBTs in this context, but the poor thermal properties of most conventional III-V materials is an undesirable feature.
Wide bandgap materials such as gallium nitride (GaN) have recently received significant attention for high frequency applications, but fundamental issues associated with substrate growth, doping, device processing, and long-term device reliability may limit their ultimate practicality. For example, aluminum gallium nitride/gallium nitride (AlGaN/GaN) HBT""s have been demonstrated, but suffer from many fundamental problems (e.g., hfe of 1.5, RIE type conversion of the base, large sheet resistance of the Mg-doped base, very poor minority carrier lifetimes in the nanosecond (ns) range). Silicon carbide, on the other hand, is a rapidly maturing semiconductor technology that has excellent thermal conductivity, high breakdown strength, and a semi-insulating (SI) substrate. An approach used to obtain better thermal dissipation in the III-V nitride devices has been to use SiC as the substrate for growth; a related approach takes advantage of the bandgap difference between AlGaN and SiC to form the AlGaN/SiC HBT, which uses SiC for the collector and base. However, using SiC substrates has not solved one of the most fundamental problems associated with nitride devices, which are the excessive defect densities present in the active devices. The defects are believed to cause (although the mechanism is not well understood) the poor reliability and scale-up of devices demonstrated to date. Current slump, proportional to the value of fI, has been observed in AlGaN/GaN devices, and scaling up to the total powers obtained by SiC devices has not been achieved.
Some attention has been given to realizing all SiC HBT""s by using different polytypes (e.g., 3C on 6H); however, there remains a need to solve the problem of difficult and impractical multiple polytype growth.
Hashimoto in U.S. Pat. No. 5,557,118 reveals an HBT in which the base is a silicon germanium (SiGe) alloy and the emitter is SiC. To avoid the intolerably large lattice mismatch between SiGe and SiC, the patent to Hashimoto reveals a graded alloy of silicon, carbon, and germanium that supposedly grades the lattice constant from the stochiometric value for SiC to the stochiometric value for the SiGe alloy used. However, it is doubtful that such an alloy is feasible, given that useful crystals with carbon content above about 8% in SiGe are difficult to grow, and even this can only be described as a xe2x80x9cpseudoalloy,xe2x80x9d as SiC does not alloy with a stochimoetry different than 50%.
The present invention includes devices and methods for fabricating all silicon carbide heterojunction bipolar transistors (HBTs) using germanium base doping to produce suitable emitter/base heterojunctions. The present invention uses a stochiometric SiC crystal throughout; the heterojuncton is formed by doping the base heavily (a few percent) with germanium (SiC:Ge), which produces a valence band offset of several hundred meV with respect to SiC. Although not as large as the valance band offset between SiC and SiGe, the offset provided by the present invention is still adequate for good HBT design. Further, the lattice mismatch is much lower (less than 1%) between SiC:Ge SiC than between SiGe and SiC, as disclosed in the prior art, providing a mismatch in the present invention that is quite tolerable.
In one embodiment of the present invention, all device layers are are grown epitaxially and the heterojunction is created by introducing a pseudoalloying material, such as germanium, with SiC, to form a graded implant. In a second embodiment, device epitaxial layers are grown directly onto a semi-insulating substrate. In a third embodiment, the semi-insulating epitaxial layer is grown onto a conducting substrate. In a fourth embodiment, the subcollector is grown on a lightly doped p-type epitaxial layer grown on a conducting substrate. In a fifth embodiment, the subcollector is grown directly on a conducting substrate.
Another embodiment of the present invention comprises a multi-finger HBT with bridging conductor connections among emitter fingers. Yet another embodiment includes growth of layers using dopants other than nitrogen or aluminum. Yet another embodiment includes use of an implantation region within one or more epitaxial layers, rather than use of separate epitaxial layers.
To achieve the stated and other advantages of the present invention, as embodied and described below, the invention includes a method for making integrated circuits having at least one heterojunction bipolar transistor, comprising: forming a semi-insulating boron-doped silicon carbide layer on a silicon carbide substrate, the semi-insulating boron-doped silicon carbide layer having a surface; forming a degeneratively doped n-type subcollector layer on the surface of the semi-insulating boron-doped silicon carbide layer; forming a doped n-type collector layer on the subcollector layer, wherein the collector layer has less doping than the subcollector layer, wherein the collector layer has a surface; forming a degeneratively doped p-type base layer on the surface of the collector layer, the base layer having a surface; and forming a doped n-type emitter layer on the surface of the base layer, the emitter layer having greater doping than the collector layer; wherein a pseudoalloying material is introduced at varying concentrations in the base layer and in the collector layer, the concentration varying from a greater concentration in the base layer to a lesser concentration in the collector layer, such that a graded junction is formed.
To achieve the stated and other advantages of the present invention, as embodied and described below, the invention further includes a method for making integrated circuits having at least one heterojunction bipolar transistor, comprising: forming a degeneratively doped n-type subcollector layer on a substrate; forming a doped n-type collector layer on the subcollector layer, wherein the collector layer has less doping than the subcollector layer, wherein the collector layer has a surface; forming a degeneratively doped p-type base layer on the surface of the collector layer, the base layer having a surface; and forming a doped n-type emitter layer on the surface of the base layer, the emitter layer having greater doping than the collector layer; wherein a pseudoalloying material is introduced at varying concentrations in the base layer and in the collector layer, the concentration varying from a greater concentration in the base layer to a lesser concentration in the collector layer, such that a graded junction is formed.
To achieve the stated and other advantages of the present invention, as embodied and described below, the invention further includes a method for making integrated circuits having at least one heterojunction bipolar transistor, comprising: forming a degeneratively doped n-type subcollector layer on the surface of a substrate, wherein the subcollector layer has a surface and at least one edge, and wherein the subcollector is bounded on at least one edge by an insulator, the insulator having a surface; forming at least one doped n-type collector layer on the subcollector layer, wherein each of the at least one collector layer has less doping than the subcollector layer, wherein the collector layer has a surface; forming a degeneratively doped p-type base layer on the surface of each of the at least one collector layer, such that at least one base layer is formed, each of the at least one base layer having a surface; forming a doped n-type emitter layer on the surface of each of the at least one base layer, such that at least one emitter layer is formed, each of the at least one emitter layer having greater doping than each of the at least one collector layer, and wherein each of the at least one emitter layer has a surface; and forming at least one conducting bridge between the surface of at least one of the at least one emitter layer and the surface of the insulator; wherein a pseudoalloying material is introduced at varying concentrations in the base layer and in the collector layer, the concentration varying from a greater concentration in the base layer to a lesser concentration in the collector layer, such that a graded junction is formed.
To achieve the stated and other advantages of the present invention, as embodied and described below, the invention further includes a method for making integrated circuits having at least one heterojunction bipolar transistor, comprising: forming a degeneratively doped n-type subcollector layer on the surface of a substrate, wherein the subcollector layer has a surface; forming a doped n-type collector layer on the subcollector layer, wherein the collector layer has less doping than the subcollector layer, wherein the collector layer has a surface and a central portion; implanting a pseudoalloying material at varying concentrations in the collector layer, the concentration varying from a lesser concentration in the central portion to a greater concentration at the collector layer surface; replacing a region of the collector layer having the implanted pseudoalloying material with a p-type base region, the p-type base region having a surface; and forming a doped n-type emitter layer on the surface of the p-type base region, the emitter layer having greater doping than the collector layer.
To achieve the stated and other advantages of the present invention, as embodied and described below, the invention further includes a heterojunction bipolar transistor, comprising: a semi-insulating boron-doped silicon carbide layer formed on a silicon carbide substrate, the semi-insulating boron-doped silicon carbide layer having a surface; a degeneratively doped n-type subcollector layer formed on the surface of the semi-insulating boron-doped silicon carbide layer; a doped n-type collector layer formed on the subcollector layer, wherein the collector layer has less doping than the subcollector layer, wherein the collector layer has a surface; a degeneratively doped p-type base layer formed on the surface of the collector layer, the base layer having a surface; and a doped n-type emitter layer formed on the surface of the base layer, the emitter layer having greater doping than the collector layer; wherein a pseudoalloying material is introduced at varying concentrations in the base layer and in the collector layer, the concentration varying from a greater concentration in the base layer to a lesser concentration in the collector layer, such that a graded junction is formed.
To achieve the stated and other advantages of the present invention, as embodied and described below, the invention further includes a heterojunction bipolar transistor, comprising: a doped n-type collector layer formed on the subcollector layer, wherein the collector layer has less doping than the subcollector layer, wherein the collector layer has a surface; a degeneratively doped p-type base layer formed on the surface of the collector layer, the base layer having a surface; and a doped n-type emitter layer formed on the surface of the base layer, the emitter layer having greater doping than the collector layer; wherein a pseudoalloying material is introduced at varying concentrations in the base layer and in the collector layer, the concentration varying from a greater concentration in the base layer to a lesser concentration in the collector layer, such that a graded junction is formed.
Additional advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become more apparent to those skilled in the art upon examination of the following or upon learning by practice of the invention.